RISC-V Architecture and DSP Processor Design Design and implement a high-performance RISC-V DSP core from ISA to SoC (Zhang Zhiwei)（Z-Library）
Science
Design a high-performance RISC-V DSP with the SpringCore architecture. Create custom ISA extensions, build an 8-stage pipelined processor, add LLVM toolchain support, debug with OpenOCD, and integrate the core into a full SoC for real-time control.
5
Views
AI Guide
AI Reading Assistant
Whole-book reading guide from stratified index samples; jump to passages in the text
No reading guide yet. Generate it on the full detail page, and it will appear here automatically.
Generate guideRecommended for You
{{#thumbnailUrl}}
{{/thumbnailUrl}}
{{^thumbnailUrl}}
{{/thumbnailUrl}}
Loading recommended books...
Failed to load, please try again later
Tip the Site
Scan the WeChat Pay or Alipay code to tip. No login required.
WeChat Pay
Alipay